1. Field of the Invention
The present invention relates generally to cascode arrangements of transistors.
2. Description of the Related Art
A cascode arrangement 10 of a main transistor 21 and a cascode transitor 22 is shown in FIG. 1. The main transistor is arranged in a common source (alternatively, common emitter) configuration which provides high signal gain and the cascode transistor is arranged in a common base (alternatively, common gate) configuration which enhances transconductance and output resistance. Accordingly, the arrangement 10 provides several important advantages (e.g., high output impedance) to a variety of circuits (e.g., current sources, current mirrors and differential amplifiers) in which it is often used.
Although referenced as a main transistor herein, the main transistor 21 is often described with other names that reflect particular applications of the cascode arrangment 10. In an amplifier application, for example, the main transistor 21 may be considered to be (and named) an input transistor that receives an input signal and, in a current source application, it may be considered to be (and named) a source transistor that generates a current.
To obtain these advantages, the main and cascode transistors must be biased to operate in the correct transistor region (e.g., saturation region of a metal-oxide-semiconductor transistor). The realization of this desired biasing is complicated by various disturbing effects (e.g., temperature and process variations) which act to alter the bias and is further complicated by the reduction of supply voltage (and, thus, dynamic range) that follows from the relentless trend in fabrication processes (e.g., from 0.35 μm to 0.25 μm to 0.18 μm and so on) that produce finer and finer integrated circuit feature sizes.
Although various structures have been proposed for biasing a cascode arrangement, they have generally permitted excessive movement of the cascode biases when subjected to the disturbing effects mentioned above.